FPGA overview	10CL016	10CL040	10CL055	10CL080	10CL120
Logic Elements	15408	39600	55856	81264	119088
Memory: M9K (kb)	504	126	260	305	432
18 x 18 Multipliers	56	126	156	244	288
PLL	Four	Four	Four	Four	Four
Maximum user I/O pins(Device)	340	325	321	289	277
Maximum user I/O pins(Board)	128	128	128	128	128

For details of the FPGA outline, see the Intel (Altera) Cyclone10 page .

• Equipped with Intel (Altera) Cyclone 10 LP FPGA 10CL016YF484, 10CL040YF484, 10CL055YF484, 10CL080YF484 or 10CL120YF484
• 3.3V single power supply operation
  Generates 2.5V and 1.2V on board
• User I/O: 128 (CNA:64 + CNB:64)
• Configuration ROM: EPCQ16A or EPCQ32A (Intel, 16/32Mbit)
• On-board clock: 50MHz (can be supplied externally)
• Connector for JTAG
  Download cable 10-pin socket
  compatible with various USB Blaster
• General-purpose LED x2
• General-purpose switch mounted x2 (DIP x1, Push x1)
• Equipped with SPI-Flash memory (Micron, 128Mbit)
• Status LED: CONF_DONE (blue), POWER LED (red)
• Built-in reset circuit for configuration

  CNA	CNB	Number of mountable terminators for LVDS	A board
  IOA0-63: MAX 27.6mm MIN 17.5mm	IOB0-63: MAX 45.4mm MIN 35.5mm	(See drawing)

  • Not all I/Os are LVDS capable
  • The user should consider each I/O standard based on the FPGA data, etc.

• 8-layer board
• Board size: 54mm x 43mm Half card size
• RoHS compliant    

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• Block Diagra
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