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Spartan-3 TQG144 equipped with breadboard

By
FPGA overviewXC3S50XC3S200XC3S400
System Gates50 K200K400 K
Logic Cells1,7284,3208,064
Maximum Distributed RAM Bits12 K30 K56 K
Total Block RAM Bits72 K216 K288 K
Maximum user I / O pins (Device)979797
Maximum user I / O pins ( Board )909090
MultipliersFour1216
DCMs2FourFour
  Equipped with XC3S50-4TQG144C or XC3S200-4TQG144C 
   or XC3S400-4TQG144C
  ■ 90 (91) I / Os are pulled out externally
  ■ Configuration ROM ( Platform Flash PROM) is standard equipment
   . Write / erase more than 20,000 times.
  clock
     48 MHz, 18.432 MHz
  ■ ISP to the configuration and ROM to the FPGA capable 7 pin JTAG connector equipped
  ■ with JTAG Buffer circuit, realized downloads stable
  ■ 3.3V single power supply
   1.2V, 2.5V to the board Generated by
  ■ Reset circuit
  ■ Credit card size    54mmX86mm ■ 4-layer board RoHS compliant